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DigiView™ Logic Analyzer Hardware Specifications


Compare DigiView™ Models

Specifications for each model of DigiView are listed below for easy comparison.

Channels 9 9 9 18 18 36
Sample Rate at Full Channels 100 200 400 100 200 250
Sample Rate at 1/2 Channels same same same Double Rate (200) Double Rate (400) Double Rate (500)
Sample period (ns) 10 5 2.5 10 @ 18 ch
  5 @ 9 ch
    5 @ 18 ch
2.5 @ 9 ch
   4 @ 36 ch
   2 @ 18 ch
Real-time Compression Yes, Tri-mode (varies according to transition frequency, duration of changes and duration of constant change)
Power Source USB External 5 VDC
(auto-reset protection)
Power (Idle / Active) <.5 Watt  / < 2.5W   < 2Watt  / < 3 Watt
Maximum voltage per Channel ±20 Volts ±50 Volts
Ground current Protection
(ground lead to ± voltage)
Yes, ±12 Volt ground variance protection with Auto Resetting fuse
Threshold Circuits 1 2
Adjustable Threshold  +0.5V to +2.8V (suitable for 0.75V to 5V logic - AGP, CCT, CMOS, GTL, GTL+, HSTL, PECL LV, SSTL, TTL) -5V to +5V
Anti-static protection Yes..., ESD protection on everything that connects to the outside world

Additional Specifications:

Channels per Cable Pod
(x Pods per unit )
9 (x 1) 9 (x 1) 9 (x 1) 9 (x 2) 9 (x 2) 9 (x 4)
Threshold Accuracy ±250mv
Trigger Output (BNC) No Yes  
Trigger position Selectable (0-100%)  
Buffer Size Selectable (1-100%)  
Raw Memory 9 Mbit
(512K x 18)
36 Mbit
(1M x 36)

Sample Depth     ( SR: Sample Rate,    DR: Data Rate,    Q: Quadrillion or 10^15 )  
    Theoretical Min
    (SR = DR)
512K x 9 512K x 9 1M x 9 512K x 18
512K x 9
512K x 18
1M x 9
1M x 36
2M x 18
    Practical Min
    (SR = 4 x DR)
1M x Channel width 2M x Channel width
    @ DR = 25Mbps (40ns) 1M x 9 2M x 9 4M x 9 1M x 18
2M x 9
2M x 18
4M x 9
4M x 36
8M x 18
    @ DR = 10Mbps (100ns) 2.5M x 9 5M x 9 10M x 9 2.5M x 18
5M x 9
5M x 18
10M x 9
10M x 36
20M x 18
    @ DR = 100Kbps (10us) 250M x 9 500M x 9 1B x 9 250M x 18
500M x 9
500M x 18
1B x 9
1B x 36
2B x 18
    @ DR = 10Kbps (100us) 2.5B x 9 5B x 9 10B x 9 2.5B x 18
5B x 9
5B x 18
10B x 9
10B x 36
20B x 18
    Theoretical Max
    (DR approaches 0)
    (Quadrillion)
3Q @ 10ns
(347 days)
3Q @ 5ns
(173 days)
6Q @ 2.5ns
(173 days)
3Q @ 10ns
(347 days)
3Q @ 5ns
(173 days)
3Q @ 5ns
6Q @ 2.5ns
(173 days)
9Q @ 4ns
18Q @ 2ns
(520 days)

Typical Captures @ Full Resolution    ( data type / count stored in hardware buffer )  
    0.1Hz clocks 87,000 262,000
    1KHz clocks 87,000 262,000
    5KHz clocks 131,000 262,000
    25MHz clocks 131,000 262,000
    Async characters 47,000 94,000
    I²C characters 10,000 20,000
    Sync characters 12,000 24,000
    8051 Bus cycles 40,000 80,000

Trigger Circuitry  
    Operating speed (MHz)  100 200 200 100 200   250
    Min Data Valid for
    Pattern Match (ns)
10 5 5 10 5 4
    Min Data Valid for
    Edge Detection (ns)
10 5 5 10 5 4

Electrical  
    Impedance >50KOhm // <10pF @ (0-3.3V)       >5KOhm // <10pF @ (<0, >3.3V) 50KOhms // < 4pF
    Connection Type, Speed USB 2.0 @ 480 Mbps

Mechanical  
    Size (LxWxH) 4.75" x 2.8" x .75" 5.0" x 4.25" x 1.40"  
    Enclosure Extruded Aluminum  


Trigger Specifications:


Trigger Sequencers   Configurable:
1@16 stages, OR 4@4 stages, OR 2@8 stages,
OR 1@8 and 2@4 stages,
OR 1@12 and 1@4 stages

 
Trigger Match Circuits   8 Universal Match Circuits. Each Circuit can be configured for any of the following:
  • Edge Detect  (Full Channel Width - OR: rising, falling, either)
  • Patterns (Full Channel Width - AND: 0, 1, X)
  • Stable (Full Channel Width)
  • > , >=, <, <=, <>   (Full Channel Width)
 
Match Duration Yes
- 1 per match circuit
- up to 1M samples each

 
Trigger Pass Count Yes (up to 1 Million per Sequencer stage)

 
Trigger Output Sources Seq 1, OR Seq 2, OR Seq 3, OR Seq4

OR (8 input sum-of-8 input products of all 8 match circuits)